1. Field of the Invention
The present invention relates to a connection structure of a flexible substrate, in particular, with measures taken therein to narrow the space between two spaced-apart solder lands formed on a counterpart substrate and thereby to facilitate reducing the size of the counterpart substrate in the case of connecting solder lands formed in both of the lateral edge portions of the flexible substrate to the two respective spaced-apart solder lands on the counterpart substrate by soldering.
2. Description of the Related Art
FIG. 6 is a plan view showing a connection structure of a flexible substrate according to a conventional example, and FIG. 7 is an illustrative enlarged cross-sectional view along the arrows VII-VII in FIG. 6. Further, FIG. 8 is a schematic plan view showing a counterpart substrate 1 according to the conventional example, and FIG. 9 is a schematic plan view showing a flexible substrate 5 according to the conventional example.
The counterpart substrate 1 in FIG. 8 is a circuit board, called PCB, with circuit patterns (not shown in the drawing) being formed on the surface of a rigid base material, the circuit patterns including electrical and electronic elements (not shown in the drawing) such as capacitors, ICs, and resistors mounted on the substrate 1 to form a predetermined control circuit as a whole.
On the other hand, the flexible substrate 5 in FIG. 9 has many parallel circuit patterns (not shown in the drawing) arranged on a base material and has flexibility as a whole, the flexibility allowing the circuit patterns to be turned relatively freely in any direction.
Then, solder lands 61 and 62 are formed in both of the lateral edge portions 51 and 52 of the flexible substrate 5 as shown in FIG. 9, and two spaced-apart solder lands 21 and 22 for soldering the respective solder lands 61 and 62 on the flexible substrate 5 thereon are formed on the counterpart substrate 1 as shown in FIG. 8. In the case of connecting the flexible substrate 5 in FIG. 9 to the counterpart substrate 1 in FIG. 8 by soldering, the space between the solder lands 21 and 22 on the counterpart substrate 1 is conventionally made equal to the space between the solder lands 61 and 62 on the flexible substrate 5 in a flat shape, and then the flexible substrate 5 is placed on the counterpart substrate 1 for soldering of the solder lands 21, 22, 61, and 62 as shown in FIG. 6. This causes the space S1 between the two spaced-apart solder lands 21 and 22 shown in FIG. 8 to be covered with the flexible substrate 5, after the connection, to be a dead space.
Meanwhile, there has been proposed a technique in which only one space for connecting multiple flexible substrates thereto is to be formed on another flexible substrate to thereby facilitate ensuring a connection space by taking measures so that the multiple flexible substrates are placed and pressed on one another when the multiple flexible substrates are connected to the another flexible substrate (refer to Japanese Patent Laid-Open Publication No. Hei 2-201992 for example).
There has also been proposed a technique in which the both sides of a main printed board are overlapped with a folded connection piece of another printed board and the overlapped portions are fastened and fixed using a screw and/or a holding metal (refer to Japanese Patent Laid-Open Publication No. Hei 5-67478 for example).
Meanwhile, it is known that PCBs like the counterpart substrate 1 shown in FIG. 6 and other figures increase in cost with an increase in the outside dimension thereof. It is therefore desired to reduce the size of the counterpart substrate 1 as small as possible and thereby to achieve cost reduction. Similarly, it is known that the flexible substrate 5 shown in FIG. 9 increases in cost with an increase in the outside dimension thereof, and therefore it is desired to reduce the size of the flexible substrate 5 as small as possible.
However, in the present circumstances, the outside dimensions of the counterpart substrate 1 and the flexible substrate 5 are reduced only by increasing the density of many circuit patterns formed thereon and/or increasing the mounting density of electrical and electronic elements as high as possible.